The invention is related to an integrated circuit (IC) design simulation and, more particularly, to a method of test pattern generation for an integrated circuit (IC) design simulation system.
Conventionally, when designing an IC, an IC design simulation system can be utilized to test the design. A test vector is composed for each set of test operations to test IC behavior. Each test vector is then compiled and linked for generation of a test pattern. The test pattern is executed to generate simulated results according to the set of test operations. The IC design simulation system comprises a test model for function simulation of the IC, and a plurality of device models for function simulation of the devices the IC are designed to connect thereto. The interactions of the IC and the devices can be simulated to verify the function of the IC.
FIG. 1 is a flowchart of a conventional method for IC design simulation. Test vectors 1˜M are composed for different sets of operations, respectively. Each test vector can comprise test configuration and test behavior. The test configuration comprises settings of the test model and device models according to the test behavior.
As shown, test vectors 1˜M are composed for different sets of operations. Test vectors 1˜M are then compiled and linked to generate test pattern 1˜M. Test pattern 1˜M is then executed, comprising configuring the test model and device models as defined by test configuration and performing the test operations defined by the test behavior. Corresponding operation record file and error log file will be generated after test pattern 1˜M execution. M times of compiling, linking and configuration time will be consumed.
Conventionally, a set of test operations requires compiling and linking time for generate a test pattern from a test vector, and configuration and execution time for performing a simulation. Multiple test operations may required when designing an IC, thus the time consumed on the compiling, linking, configuration and execution is significant.